Abstract for BMAS 2001

Designers face the challenge of specifying and implementing complicated mixed-technology systems. In order to better address mixed-signal designs, the VHDL-AMS and Verilog-AMS languages have been developed. These languages provide powerful capabilities to model and simulate behaviors in both the continuous and discrete time domains. Contemporaneously, the control systems community developed the object-oriented Modelica language to support the specification and continuous time modeling of complex control systems. The STEAMS (SUAVE and Tennessee Extensions for Analog and Mixed-Signal Systems) effort strives to provide an object-oriented systems specification and modeling language that supports both discrete and continuous time behaviors. STEAMS enables the modeling of interacting continuous and discrete time components coupled with the modeling productivity benefits associated with object-oriented techniques. This paper presents the requirements and rationale for the STEAMS language development effort, including modeling deficiencies currently facing the VHDL-AMS user community. Introduction Listing a complete set of requirements for object-oriented extensions to VHDL, a rationale for each requirement, and discussing its relative priority is not a simple task. Nonetheless, the object-oriented VHDL group needs to understand the tradeoffs and relative strengths of particular language proposals as they pertain to an independent collection of requirements. In other words, these requirements define the problem the extensions intend to address. This document extends the revised requirements document for the object-oriented VHDL study group of the IEEE Design Automation Standards Committee to support object-oriented extensions to VHDL-AMS. IEEE VHDL-AMS 1076.1-1999 specifies extensions for VHDL-1076 to add support for the description and simulation of both conservative and non-conservative continuous and mixed continuous/discrete systems. VHDL 1076.1 builds on the VHDL semantic and syntactic foundation, including structural and function decomposition, separate compilation, a powerful sequential notation and a type system. Because VHDL-AMS is based on VHDL, we first examine the requirements for VHDL and then the additional requirements for VHDL-AMS. These requirements are still very relevant to the VHDL-AMS, as it is based on the VHDL language. During the Department of Defense’s Very High Speed Integrated Circuit (VHSIC) program, the VHSIC Hardware Description Language (VHDL) development began to address essentially these needs. A perusal of the DoD Requirements for Hardware Description Languages, dated January 1983, provides interesting insight into the problems originally addressed by the VHDL development effort. These requirements from the beginning of the VHDL development can be loosely categorized into three areas: purpose/domain of use requirements, language capability/expressibility requirements, and usability/implementability requirements. The VHDL requirements from this document include: Language purpose/domain • Ability to support high level design/top-down design • Can be processed via design automation tools for